Montgomery Multiplication Coprocessor for Altera NIOS Embedded Processor

This paper describes scalable Montgomery Multiplication (MM) coprocessor optimized for Altera NIOS embedded processor implemented in reconfigurable hardware. Features of the NIOS soft processor Avalon Bus are used to connect the coprocessor as a memory mapped peripheral so that the overall performance is improved. Implemented coprocessor performs modular MM with large numbers (up to 4096 bits), the NIOS processor controls data preparation and communication with the MM unit and executes the rest of RSA algorithm operations. Various configurations of both units together with timing analysis results and area estimations for Altera devices are presented.